1 ? fn7503.2 el4583a sync separator, 50% slice, s-h, filter, h out the el4583a extracts timing from video sync in ntsc, pal, and secam systems, and non-s tandard formats, or from computer graphics operating at higher scan rates. timing adjustment is via an external resistor. input without valid vertical interval (no serration pulses) produces a default vertical output. outputs are: composite sync, ve rtical sync, filter, burst/back porch, horizontal, no signal detect, level, and odd/even output (in interlaced scan formats only). the el4583a sync slice level is set to the mid-point between sync tip and the blanking level. this 50% point is determined by two internal sample and hold circuits that track sync tip and back porch levels. it provides hum and noise rejection and compensates for input levels of 0.5v to 2.0v p-p . a built in filter attenuates the chroma signal to prevent color burst from disturbing the 50% sync slice. cut off frequency is set by a resistor to ground from the filter cut off pin. additionally, the filter can be by-passed and video signal fed directly to the video input. the level output pin provides a signal with twice the sync amplitude which may be used to control an external agc function. a ttl/cmos compatible no signal detect output flags a loss or reduction in input signal level. a resistor sets the set detect level. pinout el4583a (16-pin so) top view features ? ntsc, pal, and secam sync separation ? single supply, +5v operation ? precision 50% slicing ? built-in programmable color burst filter ? decodes non-standard vertical ? horizontal sync output ? sync pulse amplitude output ? low-power cmos ? detects loss of signal ? resistor programmable scan rate ? few external components ? available in 16-pin so (0.150?) packages ? pb-free plus anneal available (rohs compliant) applications ? video special effects ? video test equipment ? video distribution ?multimedia ? displays ?imaging ? video data capture ? video triggers analog gnd 1 2 3 4 16 15 14 13 5 6 7 12 11 10 8 9 horizontal sync out vdd odd/even output burst/back porch output rset* no signal detect output level output filter cutoff set detect level composite sync out filter input ditigal gnd vertical sync out filter output composite video input * r set must be a 1% register ordering information part number package tape & reel pkg. dwg. # el4583ais 16-pin so (0.150?) - mdp0027 el4583ais-t7 16-pin so (0.150?) 7? mdp0027 el4583ais-t13 16-pin so (0.150?) 13? mdp0027 el4583aisz (see note) 16-pin so (0.150?) (pb-free) - mdp0027 el4583aisz-t7 (see note) 16-pin so (0.150?) (pb-free) 7? mdp0027 el4583aisz-t13 (see note) 16-pin so (0.150?) (pb-free) 13? mdp0027 note: intersil pb-free plus anneal produc ts employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. data sheet caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. copyright ? intersil americas inc. 2004, 2005, 2010. all rights reserved. all other trademarks mentioned are the property of their respective owners. manufactured under u.s. patent 5,528,303. november 12, 2010
2 fn7503.2 november 12, 2010 absolute maxi mum ratings (t a = 25c) v cc supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7v storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pin voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to v cc +0.5v operating temperature range . . . . . . . . . . . . . . . . .-40c to +85c power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see curves die junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. important note: all parameters having min/max specifications are guaranteed. typical values are for information purposes only. u nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a dc electrical specifications v dd = 5v, t a = 25c, r set = 681k , r f = 33k , r lv = 82k , unless otherwise specified. parameter description min typ max unit i dd v dd = 5v (note 1) 2.5 4 ma clamp voltage pins 4, 8, unloaded 1.3 1.55 1.8 v discharge current pins 4, 8, with signal (v in = 2v) 3 6 12 a discharge current pins 4, 8, no signal (note 2) 10 a clamp charge current pins 4, 8, v in = 1v 234ma ref. voltage v ref pin 12, v dd = 5v (note 3) 1.5 1.75 2 v filter reference voltage, v fr pin 1 0.60 0.75 0.90 v level reference current pin 2 (note 4) 1.5 2.5 3.5 a v ol output low voltage i ol = 1.6ma 350 800 mv v oh output high voltage i oh = -40a 4 v i oh = -1.6ma 2.4 4 v notes: 1. no video signal, outputs unloaded 2. at loss of signal (pin 10 high) the pull down current source switches to a value of 10a 3. tested for v dd 5v 5% 4. current sourced from pin 2 is v ref /r set el4583a
3 fn7503.2 november 12, 2010 dc electrical specifications r f = 33k , r set = 681k , v dd = 5v, video input = 1v p-p , t a = 25c, c l = 15pf, i oh = -1.6ma, i ol = 1.6ma, unless otherwise specified. parameter description min typ max unit horizontal pulse width, pin 15, t h (note 1) 3.8 5 6.2 s vertical sync width, pin 5, t vs (note 2) 195 s burst/back porch width, pin 11, t b (note 1) 2.7 3.7 4.7 s filter attenuation f in = 3.6mhz (note 3) 16 db comp. sync prop. delay, t cs v in (pin 4)?comp sync 250 400 ns input dynamic range p-p ntsc signal 0.4 2 v slice level input voltage = 1v p-p 40 50 60 % v slice /v blank 40 50 60 % level out, pin 9 input voltage = 1v p-p, pin 4 500 600 700 mv vertical sync default time, t vsd (note 4) 27 36 57 s loss of signal time-out pin 10 400 600 800 s burst/back porch delay, t bd (see figure 4) 250 400 ns notes: 1. width is a function of r set 2. c/s, vertical, back porch and h are all active low, v oh = 0.8v; vertical is 3h lines wide of ntsc signal 3. attenuation is a function of r f ; see filter typical characteristics 4. vertical pulse width in absenc e of serrations on input signal el4583a
4 fn7503.2 november 12, 2010 pin descriptions pin number pin name pin function 1 filter cut-off a resistor r f connected between this input and ground determines the input filter charac teristic. increasing r f increases the filter 3.58mhz color burst attenuati on. see the typical performance characteristics. 2set detect level a resistor r lv connected between pin 2 and ground determines t he value of the minimum signal which triggers the loss of signal output on pin 10. the relationship is v p min = 0.75rlv/r set , where v p min is the minimum detected sync pulse amplitude applied to pin 4. see the typical performance characteristics. 3composite sync output this output replicates all t he sync inputs on the input video. 4 filter input the filter is a 3 pole active filter with a gain of 2, designed to produce a const ant phase delay of nominally 260 ns with signal amplitude. resistor rf on pin 1 controls the filter cut-off. an internal clamp sets the minimum voltage on pin 4 at 1.55v when the input becomes low impedance. above the clamp voltage, an input current of 1a charges the input coupling capacitor. with loss of signal, the current source swit ches to a value of 10a, for faster signal recovery. 5 vertical sync output the vertical sync output is synchronous wi th the first serration pulse rising edge in the vertical interval of the input signal and ends on the trailing edge of the first equalizing output pulse after the vertical interval. it will therefore be slightly more than 3h lines wide. 6 digital ground this is the ground return for digital buffer outputs. 7 filter output output of the active 3 pole filter which has its input on pin 4. it is recommended to ac couple the output to pin 8. 8 video input this input can be directly driven by the signal if it is desired to bypass the filter, for example, in the case of strong clean signals. this input is 6db le ss sensitive than the filter input. 9 level output this pin provides an analog vo ltage which is nominally equal to twice th e sync pulse amplitude of the video input signal applied to pin 4. it therefore pr ovides an indication of signal strength. 10 no signal detect output this is a digital output which goes high when either a) loss of input signal or b) the input signal level falls below a predetermined amplitude as set by r lv on pin 2. there will be several hori zontal lines delay before the output is initiated. 11 burst/back porch output the start of back porch output is triggered on the trailing edge of normal h sync, and on the rising edge of serration pulses in the vertical interv al. the pulse is timed out internally to produce a one-shot output. the pulse width is a function of r set . this output can be used for d.c. restore functions where the back porch level is a known reference. 12 r set the current through the resistor r set determines the timing of the functi ons within the i.c. these functions include the sampling of the sync pulse 50% point, back porch output and the 2h eliminator. for faster scan rates, the resistor needs to be reduced inversely. for ntsc 15.7khz scan rate r set is 681k 1%. r set must be a 1% resistor. 13 odd/even output odd-even output is low for even field and high for odd fiel d. the operation of this circuit has been improved for rejecting spurious noise pulses such as those present in vcr signals. 14 v dd 5v the internal circuits are designed to have a high immunity to supply vari ations, although as with most i.c.s a 0.1f decoupling capac itor is advisable. 15 horizontal sync output this output produces only true h pulses of nominal wi dth 5s. the leading edge is triggered from the leading edge of the input h sync, with the same prop. delay as the composite sync the half line pulses present in the input signal during vertical blanking are elimi nated with an internal 2h eliminator circuit. 16 analog ground this is the ground return for the signal paths in the chips, r set , r f and r lv . el4583a
5 fn7503.2 november 12, 2010 typical performance curves r set vs horizontal frequency back porch clamp on time vs r set vertical default delay time vs r set filter 3db bw vs r f level out (pin 9) vs sync tip amplitude minimum signal detect vs r lv filter attenuation vs r f @ f = 3.58mhz note: for r lv < 1000k , no signal detect output (pin 10) will default high at minimum signal sensitivit y specification, or at complete loss of signal. el4583a
6 fn7503.2 november 12, 2010 timing diagram 2 1.8 1.6 1.4 1.2 1 0.8 0.4 0.2 0 power dissipation (w) 0.6 0 25 50 75 100 125 150 ambient temperature (c) package power dissipation vs ambient temperature jedec jesd51-7 high effective thermal conductivity test board 1.563w s o 1 6 ( 0 . 1 5 0 ? ) j a = 8 0 c / w package power dissipation vs ambient temperature jedec jesd51-3 low effective thermal conductivity test board 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 255075100125150 ambient temperature (c) power dissipation (w) 85 1.136w s o 1 6 ( 0 . 1 5 0 ? ) j a = 1 1 0 c / w notes: b. the composite sync output reproduces all the video input sync pulses, with a propagation delay. c. vertical sync leading edge is coinci dent with the first vertical serration pulse leading edge, with a propagation delay. d. odd-even output is low for even field, and high for odd field. e. back porch goes low for a fixed pulse width on the trailing edge of video input sync pulses. note that for serration pulses during vertical, the back porch starts on the rising edge of the serration pulse (with propagation delay). f. horizontal sync output produces the true ?h? pulses of nominal width of 5s. it has the same delay as the composite sync. figure 1. el4583a
7 fn7503.2 november 12, 2010 figure 2. figure 3. el4583a
8 fn7503.2 november 12, 2010 description of operation a simplified block schematic is shown in figure 1. the following description is intended to provide the user with sufficient information to understand the effects of the external components and signal conditions on the outputs of the integrated circuit. the video signal is ac coupled to pin 4 via the capacitor c 1 , nominally 0.1f. the clamp circuit a1 will prevent the input signal on pin 4 going more negative than 1.5v, the value of reference voltage v r1 . thus the sync tip, the most negative part of the video waveform, will be clamped at 1.5v. the current source i 1 , nominally 6a, charges the coupling capacitor during the remaining portion of the h line, approximately 58s for a 15.75khz timebase. from i ? t = c ? v, the video time-constant can be calculated. it is important to note that the charge taken from the capacitor during video must be replaced during the sync tip time, which is much shorter, (ratio of x 12.5). the corresponding current to restore the charge during sync will therefore be an order of magnitude higher, and any resistance in series with c i will cause sync tip crushing. for this reason, the internal series resistance has been minimized and external high resistance values in series with the input coupling capacitor should be avoided. the user can exercise some control over the value of the input time constant by introducing an external pull-up resistance from pin 4 to the 5v supply. the maximum voltage across the resistance will be v dd less 1.5v, for black level. for a net discharge current greater than zero, the resistance should be greater than 450k. this will have the effect of increasing the ti me constant and reducing the degree of picture tilt. the current source i 1 directly tracks reference current i tr and thus increases with scan rate adjustment, as explained later. the signal is processed through an active 3 pole filter (f1) designed for minimum ripple with constant phase delay. the filter attenuates the color burst by 12db and eliminates fast transient spikes without sync crushing. an external filter is not necessary. the filter also amplifies the video signal by 6db to improve the detection accuracy. the filter cut-off frequency is controlled by an external resistor from pin 1 to ground. internal reference voltages (block v ref ) with high immunity to supply voltage variation are derived on the chip. reference v r4 with op-amp a2 forces pin 12 to a reference voltage of 1.7v nominal. consequently, it can be seen that the external resistance r set will determine the value of the reference current i tr . the internal resistance r3 is only about 6k , much less than r set . all the internal timing figure 4. standard (ntsc input) h. sync detail el4583a
9 fn7503.2 november 12, 2010 functions on the chip are referenced to i tr and have excellent supply voltage rejection. to improve noise immunity, the out put of the 3 pole filter is brought out to pin 7. it is recommended to ac couple the output to pin 8, the video input pin. in case of strong clean video signal, the video input pin, pin 8, can be driven by the signal directly. comparator c2 on the input to the sample and hold block (s/h) compares the leading and trailing edges of the sync pulse with a threshold voltage v r2 which is referenced at a fixed level above the clamp voltage v r1 . the output of c2 initiates the timing one-shots for gating the sample and hold circuits. the sample of the sync tip is delayed by 0.8s to enable the actual sample of 2s to be taken on the optimum section of the sync pulse tip. the acquisition time of the circuit is about three horizontal lines. the double poly cmos technology enables long time constants to be achieved with small high quality on-chip capacitors. the back porch voltage is similarly derived from the trailing edge of sync, which also serves to cut off the tip sample if the gate time exceeds the tip period. note t hat the sample and hold gating times will track r set through i ot . the 50% level of the sync tip is derived through the resistor divider r1 and r2, from the sample and held voltages v tip and v bp and applied to the plus input of comparator c1. this comparator has built in hysteresis to avoid false triggering. the output of c2 is a digital 5v signal which feeds the c/s output buffer b1, the vertical, back porch and odd/even functions. the vertical circuit senses c/s edges and initiates an integrator which is reset by the shorter horizontal sync pulses but times out with the longer vertical sync pulse widths. the internal timing circuits are referenced to i ot and v r3 , the timeout period being inversely proportional to the timing current. the vertical output pulse is started on the first serration pulse in the vertical interval and is then self-timed out. in the absence of a serration pulse, an internal timer will default the start of vertical. the horizontal circuit senses c/s edges and produces the true horizontal pulses of nominal width 5s. the leading edge is triggered from the le ading edge of the input h sync, with the same prop. delay as composite sync. the half line pulses present in the input signal during vertical blanking are removed with an internal 2h eliminator circuit. the 2h eliminator initiates a time out period after a horizontal pulse is generated. the time out period is a function of i ot which is set by r set . the back porch is triggered from the sync tip trailing edge and initiates a one-shot pulse. the period of this pulse is again a function of i ot and will therefore track the scan rate set by reset. the odd/even circuit (o/e) trac ks the relationship of the horizontal pulses to the leading edge of the vertical output and will switch on every field at the start of vertical. pin 13 is high during an odd field. loss of video signal can be detected by monitoring the no signal detect output pin 10. the vtip voltage held by the sample and hold is compared with a voltage level set by r lv on pin 2. pin 10 output goes high when the vtip falls below r lv set value. vtip voltage is also passed th rough an amplifier with gain of 2 and buffed to pin 9. this provides an indication of signal strength. this signal (level output) can be used for agc applications. el4583a
10 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn7503.2 november 12, 2010 block diagram figure 5. standard (ntsc input) h. sync detail * note: r set must be a 1% resistor el4583a
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